1. Field of the Invention
The invention relates in general to testing of integrated circuits, and more particularly, to testing of power gating circuitry.
2. Description of the Related Art
There is a growing need for enhanced power management capability in electronic devices, especially in battery-operated portable wireless devices such as cell phones, for example. Power management typically involves minimizing overall power consumption among different device functions. For applications such as cell phones that typically have long shut-down periods, power consumption typically is dominated by leakage power consumption while the device is turned off. Power gating is a technique that addresses this problem by shutting off power to circuit blocks that are not in use.
FIG. 1 is an illustrative circuit diagram of a portion of an integrated circuit 100 including typical power gating circuitry 102, 104. A first power switch transistor 102 sometimes referred to as a ‘header’ power switch, controllably couples the circuit block 106 to a VDD power supply rail 108. A second power switch transistor 104 sometimes referred to as a Tooter' power switch, controllably couples the circuit block 106 to a VSS effective ground potential rail 110. The circuit block 106, for example, may comprise combinational logic circuitry such as a CPU or DSP core, a memory and memory management unit. During operational mode, first (header) power switch transistor 102 is turned ON so as to close the switch and couple the circuit block 106 to the VDD power supply rail 108, and second (footer) power switch transistor 104 is turned ON so as to close the switch and couple the circuit block 106 to the VSS ground potential rail 110. During a sleep mode, first power switch transistor 102 is turned OFF to open the switch and decouple the circuit block 106 from the VDD power supply rail, and second power switch 104 is turned OFF so as open the switch and decouple the circuit block from the VSS ground potential rail 110.
FIG. 2 is a more detailed illustrative drawing of known header power gating circuitry 200 including the header power switch transistor 102 of FIG. 1 and a first storage circuit 202 to store a control signal to control on/off switching state of the power switch 102. In the embodiment of FIG. 2, the power switch is 102 comprises a PMOS transistor, and the storage circuitry comprises a state element like a flip-flop circuit to hold the switch value. A gate terminal 204 of the PMOS transistor 102 serves as the power switch's control terminal 204. A first bias terminal 206, which is a drain terminal in the example PMOS transistor, is coupled power source node 208. A second bias terminal, which is a second biasterminal 210 in the example PMOS transistor is coupled to a power sink node 212. More particularly, the first bias terminal 206 is coupled to the VDD power supply rail 214, and the power source node 208 represents an arbitrary location along a conductive path between the power supply rail 214 and the first bias terminal 206. The second bias terminal 210 is coupled to switched power supply terminal(s) VDDC of a gated circuit block (not shown) that is, i.e. a block that is switched on/off by the power switch 102. The power sink node 212 represents an arbitrary location along a conductive path between the second bias terminal 210 and the switched power supply terminal(s) VDDC. When the switch 102 is closed, power is ‘sourced’ from the VDD power to the switch and ‘sinked’ from the switch 102 to the switched power supply terminal(s) VDDC of the circuit block in order to power-up the circuitry within the block.
The storage circuit 202 has an unswitched connection to the VDD power supply. In operation, when the switched power supply VDDC is to be powered-up through VDD, a logical ‘0’ is latched in the flip-flop 202, and the PMOS power switch 102 is turned ON, i.e. the switch 102 is closed, and a path from the first bias terminal 206 to the second bias terminal 210 is established. When the switched power supply VDDC is to be cutoff from the VDD, a logical ‘1’ is latched in the flip-flop 202, and the PMOS switch 102 is turned OFF, i.e. the switch 102 is opened, and a path between VDD and VDDC is cutoff.
As explained with reference to FIG. 1, power gating circuitry ordinarily operates by selectively isolating the gated logic from both the power supply and from ground potential. Accordingly, footer power gating circuitry (not shown) typically is provided that basically has the same circuit topology as the header power gating circuitry 200 of FIG. 2. The operation of such footer power gating circuitry will be readily appreciated by persons of ordinary skill in the art from the above description of the operation of the header power gating circuitry 200. Alternatively, the header power switch can be an NMOS transistor and the footer power switch can include a PMOS transistor.
FIG. 3 is an illustrative drawing of the known power gating circuitry 200 of FIG. 2 that exhibits an ‘always-ON’ defect, which is represented by dashed lines 302 between the first and second terminals 206, 210. Unfortunately, manufacturing defects are not uncommon occurrences in the production of integrated circuit devices. One type of defect causes a switch, such as illustrative switch power switch 102, to be always in turned-ON state. The dashed lines 302 represent a manufacturing defect that causes the power switch to be always-ON in that there is a permanent connection between the first and second terminals 206, 210, and therefore, between the source and sink nodes 208, 212, and also between the supply voltage VDD and the switched supply VDDC. In other words, due to a manufacturing defect the first bias terminal 206 and the second bias terminal 210 of the PMOS transistor 102 are shorted together, and as a result the logical state of a control signal applied to the gate terminal 204 cannot be used to turn-OFF the switch 102. Because of this always-ON behavior, current may be drawn from the power supply VDD by a circuitry (not shown) that is intended to be turned off and when in a sleep mode, thus decreasing the battery life if the device is a battery operated device. Moreover, if the package for such integrated circuit device is not designed to handle such always-ON activity then, due to the fault in the power switch there could be over-heating of the device that could lead to meltdown and device failure in the field. Hence, the condition of the power switch being always ON can be a critical fault that should be detected during the manufacturing test.
Moreover, the illustrative power switch 102 also is susceptible to manufacturing defects causing the switch to be always-OFF. Over time, such always-OFF defect in a power switch can eventually lead to an accumulation of charge, causing the switch 102 to convert to always-ON behavior resulting in the power drain and overheating problems described above, for example.
Unfortunately, defects in power switch circuitry are so called ‘soft’ defects that do not ordinarily show up as a failure during testing, but nevertheless, can prevent a device from entering into a deep sleep or power saving mode, leading to shorter battery life and reduced quality of the device. Specifically, we refer to these as soft defects because unlike a ‘hard’ manufacturing defects that would cause incorrect operation of the circuit during normal powered-up operation and hence rendering the chip useless, a defect in the power switch part of a circuit will not render the device useless because it does not affect the functionality during normal operation. Nevertheless, this is a defect because, a circuit that is supposed to be sleeping and saving power so as to extend battery life would be active and dissipating power, which could lead to shorter battery life and hence not meeting the stated power saving device specifications. Unfortunately, the above-described type of defect is not detected by typical ATPG and functional tests.
Thus, there has been a need to detect manufacturing defects in power switch circuitry. The present invention meets this need.